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FEATURES Throughput: 100 kSPS INL: 3 LSB Max ( 0.0046% of Full-Scale) 16 Bits Resolution with No Missing Codes S/(N+D): 87 dB Min, 90 dB Typ @ 10 kHz THD: -96 dB Max @ 10 kHz Analog Input Voltage Range: 0 V to 2.5 V Both AC and DC Specifications No Pipeline Delay Parallel and Serial 5 V/3 V Interface Single 5 V Supply Operation 21 mW Typical Power Dissipation, 21 W @ 100 SPS Power-Down Mode: 7 W Max Package: 48-Lead Quad Flatpack (LQFP) Pin-to-Pin Compatible with the AD7664 APPLICATIONS Data Acquisition Battery-Powered Systems PCMCIA Instrumentation Automatic Test Equipment Scanners Medical Instruments Process Control
IN INGND
16-Bit, 100 kSPS CMOS ADC AD7660*
FUNCTIONAL BLOCK DIAGRAM
AVDD AGND REF REFGND DVDD DGND OVDD SERIAL PORT SWITCHED CAP DAC 16 DATA[15:0] BUSY PARALLEL INTERFACE PD RESET CLOCK CONTROL LOGIC AND CALIBRATION CIRCUITRY RD CS SER/PAR OB/2C OGND
AD7660
CNVST
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD7660 is a 16-bit, 100 kSPS, charge redistribution SAR, analog-to-digital converter that operates from a single 5 V power supply. The part contains an internal conversion clock, error correction circuits, and both serial and parallel system interface ports. The AD7660 is hardware factory calibrated and is comprehensively tested to ensure such ac parameters as signal-to-noise ratio (SNR) and total harmonic distortion (THD), in addition to the more traditional dc parameters of gain, offset, and linearity. It is fabricated using Analog Devices' high-performance, 0.6 micron CMOS process with correspondingly low cost, and is available in a 48-lead LQFP with operation specified from -40C to +85C.
1. Fast Throughput The AD7660 is a 100 kSPS, charge redistribution, 16-bit SAR ADC with internal error correction circuitry. 2. Superior INL The AD7660 has a maximum integral nonlinearity of 3 LSBs with no missing 16-bit code. 3. Single-Supply Operation The AD7660 operates from a single 5 V supply and only dissipates 21 mW typical. Its power dissipation decreases with the throughput to, for instance, only 21 W at a 100 SPS throughput. It consumes 7 W maximum when in power-down. 4. Serial or Parallel Interface Versatile parallel or 2-wire serial interface arrangement compatible with both 3 V or 5 V logic.
*Patent pending.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2000
AD7660-SPECIFICATIONS (-40 C to +85 C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
Parameter RESOLUTION ANALOG INPUT Voltage Range Operating Input Voltage Analog Input CMRR Leakage Current at 25C Input Impedance THROUGHPUT SPEED Complete Cycle Throughput Rate DC ACCURACY Integral Linearity Error Differential Linearity Error No Missing Codes Transition Noise 2 Full-Scale Error3 Unipolar Zero Error3 Power Supply Sensitivity AC ACCURACY Signal-to-Noise Spurious Free Dynamic Range Total Harmonic Distortion Signal-to-(Noise+Distortion) -3 dB Input Bandwidth SAMPLING DYNAMICS Aperture Delay Aperture Jitter Transient Response REFERENCE External Reference Voltage Range External Reference Current Drain POWER SUPPLIES Specified Performance AVDD DVDD OVDD Operating Current AVDD DVDD5 OVDD5 Power Dissipation5 VIN - VINGND VIN VINGND fIN = 25 kHz 100 kSPS Throughput Conditions Min 16 0 -0.1 -0.1 70 325 See Analog Input Section 10 100 +3 +1.75 0.75 0.09 1 3 87 96 87 30 820 2 5 Full-Scale Step 2.3 100 kSPS Throughput 2.5 22 8 2.7 90 -96 0.16 5 VREF +3 +0.5 Typ Max Unit Bits V V V dB nA
0 -3 -1 16 REF = 2.5 V AVDD = 5 V 5% fIN = 10 kHz fIN = 10 kHz fIN = 10 kHz fIN = 10 kHz -60 dB Input
s kSPS LSB1 LSB Bits LSB % of FSR LSB LSB dB4 dB dB dB dB kHz ns ps rms s V A
4.75 4.75 2.7 100 kSPS Throughput
5 5
5.25 5.25 5.25
V V V mA mA A mW W W
100 kSPS Throughput 100 SPS Throughput in Power-Down Mode 5, 6
3.2 1 10 21 21
25 7
DIGITAL INPUTS Logic Levels VIL VIH IIL IIH DIGITAL OUTPUTS Data Format Pipeline Delay VOL VOH TEMPERATURE RANGE Specified Performance ISINK = 1.6 mA ISOURCE = -500 A TMIN to TMAX
-0.3 +2.0 -1 -1
+0.8 OVDD + 0.3 +1 +1
V V A A
Parallel or Serial 16-Bit Conversion Results Available Immediately after Completed Conversion 0.4 OVDD - 0.6 -40 +85
V V C
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AD7660
NOTES 1 LSB means Least Significant Bit. With the 0 V to 2.5 V input range, one LSB is 38.15 V. 2 Typical rms noise at worst-case transitions and temperatures. 3 See Definition of Specifications section. These specifications do not include the error contribution from the external reference. 4 All specifications in dB are referred to a full-scale input F S. Tested with an input signal at 0.5 dB below full-scale unless otherwise specified. 5 Tested in parallel reading mode. 6 With all digital inputs forced to DVDD or DGND respectively. Specifications subject to change without notice.
TIMING SPECIFICATIONS (-40 C to +85 C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
Symbol Refer to Figures 11 and 12 Convert Pulsewidth Time Between Conversions CNVST LOW to BUSY HIGH Delay BUSY HIGH All Modes Except in Master Serial Read after Convert Mode Aperture Delay End of Conversion to BUSY LOW Delay Conversion Time Acquisition Time RESET Pulsewidth Refer to Figures 13, 14, and 15 (Parallel Interface Modes) CNVST LOW to DATA Valid Delay DATA Valid to BUSY LOW Delay Bus Access Request to DATA Valid Bus Relinquish Time Refer to Figures 16, and 17 (Master Serial Interface Modes) 1 CS LOW to SYNC Valid Delay CS LOW to Internal SCLK Valid Delay CS LOW to SDOUT Delay CNVST LOW to SYNC Delay SYNC Asserted to SCLK First Edge Delay Internal SCLK Period Internal SCLK HIGH (INVSCLK Low) 2 Internal SCLK LOW (INVSCLK Low) 2 SDOUT Valid Setup Time SDOUT Valid Hold Time SCLK Last Edge to SYNC Delay CS HIGH to SYNC HI-Z CS HIGH to Internal SCLK HI-Z CS HIGH to SDOUT HI-Z BUSY HIGH in Master Serial Read after Convert CNVST LOW to SYNC Asserted Delay SYNC Deasserted to BUSY LOW Delay Refer to Figures 18 and 20 (Slave Serial Interface Modes) 1 External SCLK Setup Time External SCLK Active Edge to SDOUT Delay SDIN Setup Time SDIN Hold Time External SCLK Period External SCLK HIGH External SCLK LOW t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 t28 t29 t30 t31 t32 t33 t34 t35 t36 t37 Min 5 10 15 2 2 10 2 8 10 2 45 5 40 50 10 10 10 0.5 4 40 30 9.5 4.5 3 3 75 Typ Max Unit ns s ns s ns ns s s ns s ns ns ns ns ns ns s ns ns ns ns ns ns ns ns ns s s ns ns ns ns ns ns ns ns
10 10 10 3.2 1.5 50 5 3 5 5 25 10 10
16
NOTES 1 In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C L of 10 pF; otherwise, the load is 60 pF maximum. 2 If the polarity of SCLK is inverted, the timing references of SCLK are also inverted. Specifications subject to change without notice.
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AD7660
ABSOLUTE MAXIMUM RATINGS 1
Analog Inputs IN2, REF . . . . . . . . . . . . AVDD + 0.3 V to AGND - 0.3 V INGND, REFGND . . . . . . . . . . . . . . . . . . AGND 0.3 V Ground Voltage Differences AGND, DGND, OGND . . . . . . . . . . . . . . . . . . . . . 0.3 V Supply Voltages AVDD, DVDD, OVDD . . . . . . . . . . . . . . . . . . . . . . . . 7 V AVDD to DVDD, AVDD to OVDD . . . . . . . . . . . . . . 7 V DVDD to OVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Digital Inputs Except the Data Bus D(7:4) . . . -0.3 V to DVDD + 0.3 V Data Bus Inputs D(7:4) . . . . . . -0.3 V to OVDD + 0.3 V Internal Power Dissipation3 . . . . . . . . . . . . . . . . . . . 700 mW Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature Range (Soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 300C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 See Analog Input section. 3 Specification is for device in free air: 48-Lead LQFP: JA = 91C/W, JC = 30C/W.
PIN CONFIGURATION 48-Lead LQFP (ST-48)
REFGND REF INGND NC NC NC NC NC NC NC NC NC
48 47 46 45 44 43 42 41 40 39 38 37
AGND 1 AVDD 2 NC 3 DGND 4 OB/2C 5 NC 6 NC 7 SER/PAR 8 D0 9 D1 10 D2 11 D3 12 NC = NO CONNECT
PIN 1 IDENTIFIER
36 35 34 33 32
AGND CNVST PD RESET CS
AD7660
TOP VIEW (Not to Scale)
RD DGND 29 BUSY
31 30 28 27 26 25
D15 D14 D13 D12
13 14 15 16 17 18 19 20 21 22 23 24
D7/RDC/SDIN OGND
DVDD DGND
OVDD
D4/EXT/INT D5/INVSYNC D6/INVSCLK
D8/SDOUT
D9/SCLK D10/SYNC
1.6mA
IOL
TO OUTPUT PIN
1.4V CL 60pF1 500 A IOH
0.8V 2V
NOTE: 1IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD CL OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
tDELAY
2V 0.8V
tDELAY
2V 0.8V
Figure 1. Load Circuit for Digital Interface Timing
Figure 2. Voltage Reference Levels for Timings
ORDERING GUIDE
Model AD7660AST AD7660ASTRL EVAL-AD7660CB1 EVAL-CONTROL BOARD2
Temperature Range -40C to +85C -40C to +85C
Package Description Quad Flatpack (LQFP) Quad Flatpack (LQFP) Evaluation Board Controller Board
Package Option ST-48 ST-48
NOTES 1 This board can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONTROL BOARD for evaluation/demonstration purposes. 2 This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7660 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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D11/RDERROR
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PIN FUNCTION DESCRIPTIONS
Pin No. 1 2 3, 6, 7, 40-48 4 5
Mnemonic AGND AVDD NC DGND OB/2C
Type P P
Description Analog Power Ground Pin. Input Analog Power Pins. Nominally 5 V. No Connect. Must be tied to digital ground. Straight Binary/Binary Two's Complement. When OB/2C is HIGH, the digital output is straight binary; when LOW, the MSB is inverted resulting in a two's complement output from its internal shift register. Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the serial interface mode is selected and some bits of the DATA bus are used as a serial port. Bit 0 to Bit 3 of the Parallel Port Data Output Bus. These pins are always outputs regardless of the state of SER/PAR. When SER/PAR is LOW, this output is used as the Bit 4 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this input, part of the serial port, is used as a digital select input for choosing the internal or an external data clock. With EXT/INT tied LOW, the internal clock is selected on SCLK output. With EXT/INT set to a logic HIGH, output data is synchronized to an external clock signal connected to the SCLK input. When SER/PAR is LOW, this output is used as the Bit 5 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this input, part of the serial port, is used to select the active state of the SYNC signal. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW. When SER/PAR is LOW, this output is used as the Bit 6 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this input, part of the serial port, is used to invert the SCLK signal. It is active in both master and slave mode. When SER/PAR is LOW, this output is used as the Bit 7 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this input, part of the serial port, is used as either an external data input or a read mode selection input depending on the state of EXT/INT. When EXT/INT is HIGH, RDC/SDIN could be used as a data input to daisy chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on DATA with a delay of 16 SCLK periods after the initiation of the read sequence. When EXT/INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is HIGH, the data is output on SDOUT during conversion. When RDC/SDIN is LOW, the data is output on SDOUT only when the conversion is complete. Input/Output interface Digital Power Ground. Input/Output interface Digital Power. Nominally at the same supply than the supply of the host interface (5 V or 3 V). Digital Power. Nominally at 5 V. Digital Power Ground. When SER/PAR is LOW, this output is used as the Bit 8 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this output, part of the serial port, is used as a serial data output synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7660 provides the conversion result, MSB first, from its internal shift register. The DATA format is determined by the logic level of OB/2C. In serial mode, when EXT/INT is LOW, SDOUT is valid on both edges of SCLK. In serial mode, when EXT/INT is HIGH: If INVSCLK is LOW, SDOUT is updated on SCLK rising edge and valid on the next falling edge. If INVSCLK is HIGH, SDOUT is updated on SCLK falling edge and valid on the next rising edge.
DI DI
8 9-12 13
SER/PAR DATA[0:3] DATA[4] or EXT/INT
DI DO DI/O
14
DATA[5] or INVSYNC DATA[6] or INVSCLK DATA[7] or RDC/SDIN
DI/O
15
DI/O
16
DI/O
17 18 19 20 21
OGND OVDD DVDD DGND DATA[8] or SDOUT
P P P P DO
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AD7660
Pin No. 22 Mnemonic DATA[9] or SCLK Type DI/O Description When SER/PAR is LOW, this output is used as the Bit 9 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this pin, part of the serial port, is used as a serial data clock input or output, dependent upon the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated depends upon the logic state of the INVSCLK pin. When SER/PAR is LOW, this output is used as the Bit 10 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this output, part of the serial port, is used as a digital output frame synchronization for use with the internal data clock (EXT/INT = Logic LOW). When a read sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH while SDOUT output is valid. When a read sequence is initiated and INVSYNC is High, SYNC is driven LOW and remains LOW while SDOUT output is valid. When SER/PAR is LOW, this output is used as the Bit 11 of the Parallel Port Data Output Bus. When SER/PAR is HIGH and EXT/INT is HIGH, this output, part of the serial port, is used as an incomplete read error flag. In slave mode, when a data read is started and not complete when the following conversion is complete, the current data is lost and RDERROR is pulsed high. Bit 12 to Bit 15 of the Parallel Port Data output bus. These pins are always outputs regardless of the state of SER/PAR. Busy Output. Transitions HIGH when a conversion is started, and remains HIGH until the conversion is complete and the data is latched into the on-chip shift register. The falling edge of BUSY could be used as a data ready clock signal.
Must be tied to digital ground.
23
DATA[10] or SYNC
DO
24
DATA[11] or RDERROR
DO
25-28 29
DATA[12:15] BUSY
DO DO
30
DGND
P
31 32 33 34 35
RD CS RESET PD CNVST
DI DI DI DI DI
36 37 38 39 43
AGND REF REFGND INGND IN
P AI AI AI AI
Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. RD and CS are OR'd together internally. Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. RD and CS are OR'd together internally. Reset Input. When set to a logic HIGH, reset the AD7660. Current conversion if any is aborted. Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions are inhibited after the current one is completed. Start Conversion. If CNVST is HIGH when the acquisition phase (t8) is complete, the next falling edge on CNVST puts the internal sample/hold into the hold state and initiates a conversion. This mode is the most appropriate if low sampling jitter is desired. If CNVST is LOW when the acquisition phase (t8) is complete, the internal sample/hold is put into the hold state and a conversion is immediately started. Must be tied to analog ground. Reference Input Voltage. Reference Input Analog Ground. Analog Input Ground. Primary analog input with a range of 0 V to VREF.
NOTES AI = Analog Input DI = Digital Input DI/O = Bidirectional Digital DO = Digital Output P = Power
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AD7660
DEFINITION OF SPECIFICATIONS INTEGRAL NONLINEARITY ERROR (INL) TOTAL HARMONIC DISTORTION (THD)
Linearity error refers to the deviation of each individual code from a line drawn from "negative full scale" through "positive full scale." The point used as "negative full scale" occurs 1/2 LSB before the first code transition. "Positive full scale" is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line.
DIFFERENTIAL NONLINEARITY ERROR (DNL)
THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels.
SIGNAL-TO-NOISE RATIO (SNR)
SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels.
SIGNAL TO (NOISE AND DISTORTION) RATIO (S/[N+D])
In an ideal ADC, code transitions are 1 LSB apart. Differential nonlinearity is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed.
FULL-SCALE ERROR
The last transition (from 011 . . . 10 to 011 . . . 11 in two's complement coding) should occur for an analog voltage 1 1/2 LSB below the nominal full scale (2.49994278 V for the 0 V-2.5 V range). The full-scale error is the deviation of the actual level of the last transition from the ideal level.
UNIPOLAR ZERO ERROR
S/(N+D) is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/(N+D) is expressed in decibels.
APERTURE DELAY
Aperture delay is a measure of the acquisition performance, and is measured from the falling edge of the CNVST input to when the input signal is held for a conversion.
TRANSIENT RESPONSE
The first transition should occur at a level 1/2 LSB above analog ground (19.073 V for the 0 V-2.5 V range). Unipolar zero error is the deviation of the actual transition from that point.
SPURIOUS FREE DYNAMIC RANGE (SFDR)
The time required for the AD7660 to achieve its rated accuracy after a full-scale step function is applied to its input.
The difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal.
EFFECTIVE NUMBER OF BITS (ENOB)
ENOB is a measurement of the resolution with a sine wave input. It is related to S/[N+D] by the following formula: ENOB = (S/[N+D]dB - 1.76)/6.02 and is expressed in bits.
REV. 0
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AD7660-Typical Performance Characteristics
3
1.75 1.50
2
1.25 1.00
1
DNL - LSB
0.75 0.50 0.25 0.00
INL - LSB
0
-1
-0.25
-2
-0.50 -0.75
-3
-1.00
0 16384 32768 CODE 49152 65536
0
16384
32768 CODE
49152
65536
TPC 1. Integral Nonlinearity vs. Code
TPC 4. Differential Nonlinearity vs. Code
35
30
30
25
NUMBER OF UNITS
20
NUMBER OF UNITS
25
20 15
15
10
10 5 0 -3.0
5
0
0
0.6
1.2 1.8 POSITIVE INL - LSB
2.4
3.0
-2.4
-1.8 -1.2 NEGATIVE INL - LSB
-0.6
0
TPC 2. Typical Positive INL Distribution (350 Units)
TPC 5. Typical Negative INL Distribution (350 Units)
8000 7219 7000 7051
10000 9026 8000
6000 5000
6000
COUNTS
4000 3000 2000 1213 879 1000 0 0 0 13 9 0 0
COUNTS
4000
3489
3520
2000
0 0
0
161
188
0 8010
0 8011
8008 8009 800A 800B 800C 800D 800E 800F 8010 8011 CODE - Hexa
8009 800A 800B 800C 800D 800E 800F CODE - Hexa
TPC 3. Histogram of 16,384 Conversions of a DC Input at the Code Transition
TPC 6. Histogram of 16,384 Conversions of a DC Input at the Code Center
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AD7660
0 -20
AMPLITUDE - dB (Full Scale)
100 4096 POINT FFT FS = 100kHz fIN = 10.02kHz, -0.5dB SNR = 89.8dB SINAD = 89.4dB THD = -99.3dB SFDR = 101.6dB
16.0
95
SNR AND S/[N+D] - dB
15.5
-40 -60 -80 -100 -120 -140
90 SNR 85 S/(N+D) 80 ENOB 75
15.0
ENOB - Bits
14.5
14.0
13.5
-160 -180 70 0 10 20 30 40 50 0 FREQUENCY - kHz 100k 10k FREQUENCY - Hz 13.0 1M
TPC 7. FFT Plot
TPC 10. SNR, S/(N+D), and ENOB vs. Frequency
-60 SFDR -70
110
92
100
SNR (REFERRED TO FULL SCALE) - dB
THD, HARMONICS - dB
90
90
-90
80
SFDR - dB
-80
88
THD -100 3RD HARMONIC -110
2ND HARMONIC
70
60 0 100k 10k FREQUENCY - Hz 1M
86 -60
-50
-40 -30 -20 INPUT LEVEL - dB
-10
0
TPC 8. THD, Harmonics, and SFDR vs. Frequency
TPC 11. SNR vs. Input Level
-60
50 OVDD = 2.7V, 85 C 40
THD, HARMONICS - dB
-80
t12 DELAY - ns
30
OVDD = 2.7V, 25 C
-100 2ND HARMONIC THD
20 OVDD = 5V, 85 C
-120
10 OVDD = 5V, 25 C
3RD HARMONIC -140 -90
0 0
-80
-70
-60
-50 -40 -30 INPUT LEVEL - dB
-20
-10
0
50
100 CL - pF
150
200
TPC 9. THD, Harmonics vs. Input Level
TPC 12. Typical Delay vs. Load Capacitance CL
REV. 0
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AD7660
10000000
100
POWER-DOWN OPERATING CURRENTS - nA
AVDD
90 80 70 60 50 40 30 20 DVDD 10 0 -50 OVDD AVDD
1000000
OPERATING CURRENTS - nA
DVDD 100000
10000 OVDD 1000
100 10 1 0.1
1
10
100 1000 10000 SAMPLING RATE - SPS
100000 1000000
-25
0 25 50 TEMPERATURE - C
75
100
TPC 13. Operating Currents vs. Sample Rate
TPC 14. Power-Down Operating Currents vs. Temperature
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AD7660
IN REF REFGND MSB 32768C 16384C 4C 2C C LSB C BUSY COMP INGND 67536C SWB CNVST CONTROL LOGIC OUTPUT CODE LSB SWA SWITCHES CONTROL
Figure 3. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD7660 provides the user with an on-chip track/hold, successive approximation ADC that does not exhibit any pipeline or latency, making it ideal for multiple multiplexed channel applications. The AD7660 can be operated from a single 5 V supply and be interfaced to either 5 V or 3 V digital logic. It is housed in a 48-lead LQFP package that combines space savings and allows flexible configurations as either serial or parallel interface. The AD7660 is pin-to-pin-compatible with the AD7664.
CONVERTER OPERATION
ADC CODE - Straight Binary
The AD7660 is a fast, low-power, single-supply, precise 16-bit analog-to-digital converter (ADC). The AD7660 is capable of converting 100,000 samples per second (100 kSPS) and allows power saving between conversions. When operating at 100 SPS, for example, it consumes typically only 21 W. This feature makes the AD7660 ideal for battery-powered applications.
1 LSB = VREF/65536 111...111 111...110 111...101
000...010 000...001 000...000 0V 1 LSB 0.5 LSB VREF -1 LSB VREF -1.5 LSB ANALOG INPUT
Figure 4. ADC Ideal Transfer Function
Transfer Functions
The AD7660 is a successive approximation analog-to-digital converter based on a charge redistribution DAC. Figure 3 shows the simplified schematic of the ADC. The capacitive DAC consists of an array of 16 binary weighted capacitors and an additional "LSB" capacitor. The comparator's negative input is connected to a "dummy" capacitor of the same value as the capacitive DAC array. During the acquisition phase, the common terminal of the array tied to the comparator's positive input is connected to AGND via SWA. All independent switches are connected to the analog input IN. Thus, the capacitor array is used as a sampling capacitor and acquires the analog signal on IN input. Similarly, the "dummy" capacitor acquires the analog signal on INGND input. When the acquisition phase is complete and the CNVST input goes or is low, a conversion phase is initiated. When the conversion phase begins, SWA and SWB are opened first. The capacitor array and the "dummy" capacitor are then disconnected from the inputs and connected to the REFGND input. Therefore, the differential voltage between IN and INGND captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between REFGND or REF, the comparator input varies by binary weighted voltage steps (VREF/2, VREF/4 . . . VREF/65536). The control logic toggles these switches, starting with the MSB first, in order to bring the comparator back into a balanced condition. After the completion of this process, the control logic generates the ADC output code and brings BUSY output low. REV. 0
Using the OB/2C digital input, the AD7660 offers two output codings: straight binary and two's complement. The LSB size is VREF/65536, which is about 38.15 V. The ideal transfer characteristic for the AD7660 is shown in Figure 4 and Table I.
Table I. Output Codes and Ideal Input Voltages
Description
Analog Input
Digital Output Code (Hexa) Straight Two's Binary Complement FFFF1 FFFE 8001 8000 7FFF 0001 00002 7FFF1 7FFE 0001 0000 FFFF 8001 80002
FSR - 1 LSB 2.499962 V FSR - 2 LSB 2.499923 V Midscale + 1 LSB 1.250038 V Midscale 1.25 V Midscale - 1 LSB 1.249962 V -FSR + 1 LSB 38 V -FSR 0V
NOTES 1 This is also the code for overrange analog input (V IN - VINGND above VREF - VREFGND). 2 This is also the code for underrange analog input (V IN below VINGND).
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AD7660
TYPICAL CONNECTION DIAGRAM
Figure 6 shows a typical connection diagram for the AD7660.
AVDD D1 IN OR INGND C1 R1 C2
80 70 60 50 40 30
AGND
Figure 5. Equivalent Analog Input Circuit
20
Analog Input
CMRR - dB
D2
Figure 5 shows an equivalent circuit of the input structure of the AD7660. The two diodes D1 and D2 provide ESD protection for the analog inputs IN and INGND. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 0.3 V. This will cause these diodes to become forward-biased and start conducting current. These diodes can handle a forward-biased current of 100 mA maximum. For instance, these conditions could eventually occur when the input buffer's (U1) supplies are different from AVDD. In such case, an input buffer with a short circuit current limitation can be used to protect the part. This analog input structure allows the sampling of the differential signal between IN and INGND. Unlike other converters, the INGND input is sampled at the same time as the IN input. By using this differential input, small signals common to both inputs are rejected as shown in Figure 7 which represents the typical CMR over frequency. For instance, by using INGND to sense a remote signal ground, difference of ground potentials between the sensor and the local ADC ground are eliminated.
ANALOG SUPPLY (5V) 100 10 F 100nF 10 F 100nF
10 0 0.1k
1k 10k 100k 1M COMMON-MODE INPUT FREQUENCY - Hz
10M
Figure 7. Analog Input CMR vs. Frequency
During the acquisition phase, the impedance of the analog input IN can be modeled as a parallel combination of capacitor C1 and the network formed by the series connection of R1 and C2. Capacitor C1 is primarily the pin capacitance. The resistor R1 is typically 3242 and is a lumped component made up of some serial resistor and the on resistance of the switches. The capacitor C2 is typically 60 pF and is mainly the ADC sampling capacitor. During the conversion phase, where the switches are opened, the input impedance is limited to C1. It has to be noted that the input impedance of the AD7660, unlike other SAR ADCs, is not a pure capacitance and thus, inherently reduces the kickback transient at the beginning of the acquisition phase. The R1, C2 makes a one-pole low-pass filter that reduces undesirable aliasing effect and limits the noise.
100nF
10 F
DIGITAL SUPPLY (3.3V OR 5V)
AVDD 2.5V REF1 CREF1 100nF REFGND REF
AGND
DGND
DVDD
OVDD
OGND SCLK SDOUT
SERIAL PORT
BUSY U12
AD7660
IN CNVST OB/2C INGND SER/PAR CS PD RESET RD CLOCK DVDD D3
C/ P/DSP
ANALOG INPUT (0V TO 2.5V)
NOTES: 1WITH THE AD780 OR THE ADR291 VOLTAGE REFERENCE, C REF IS 47 F 2THE AD8519 IS RECOMMENDED 3OPTIONAL LOW JITTER CNVST
Figure 6. Typical Connection Diagram
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REV. 0
AD7660
When the source impedance of the driving circuit is low, the AD7660 can be driven directly. Large source impedances will significantly affect the ac performances, especially the total harmonic distortion. The maximum source impedance depends on the amount of total harmonic distortion (THD) that can be tolerated. The THD degrades in function of the source impedance and the maximum input frequency as shown in Figure 8.
-70 RS = 500 -75
and REFGND inputs. This decoupling depends on the choice of the voltage reference but, usually consists of a low ESR tantalum capacitor and a 100 nF ceramic capacitor. Appropriate value for the tantalum capacitor is 47 F with the low-cost, low-power ADR291 voltage reference or with the low-noise, low-drift AD780 voltage reference. For applications using multiple AD7660s, it is more effective to buffer the reference voltage with a low-noise, very stable op amp like the AD8031. Care should also be taken with the reference temperature coefficient of the voltage reference which directly affects the full-scale accuracy if this parameter matters. For instance, a 15 ppm/C tempco of the reference changes the full scale by 1 LSB/C.
Power Supply
-80
THD - dB
-85
RS = 100
-90
RS = 50
-95
RS = 20
-100 1 10 INPUT FREQUENCY - kHz 100
Figure 8. THD vs. Analog Input Frequency and Input Resistance
Driver Amplifier Choice
The AD7660 uses three sets of power supply pins: an analog 5 V supply AVDD, a digital 5 V core supply DVDD, and a digital input/output interface supply OVDD. The OVDD supply allows direct interface with any logic working between 2.7 V and 5.25 V. To reduce the number of supplies needed, the digital core (DVDD) can be supplied through a simple RC filter from the analog supply as shown in Figure 6. The AD7660 is independent of power supply sequencing and thus free from supply voltage induced latchup. Additionally, it is very insensitive to power supply variations over a wide frequency range as shown in Figure 9.
-50
Although the AD7660 is easy to drive, the driver amplifier needs to meet at least the following requirements: * The driver amplifier and the AD7660 analog input circuit have to be able together to settle for a full-scale step the capacitor array at a 16-bit level (0.0015%). For instance, operation at the maximum throughput of 100 kSPS requires a minimum gain bandwidth product of 5 MHz. * The noise generated by the driver amplifier needs to be kept as low as possible in order to preserve the SNR and transition noise performance of the AD7660. The noise coming from the driver is filtered by the AD7660 analog input circuit one-pole low-pass filter made by R1 and C2. For instance, a driver with an equivalent input noise of 7 nV/Hz like the AD8519 and configured as a buffer, thus with a noise gain of +1, degrades the SNR by only 0.2 dB. * The driver needs to have a THD performance suitable to that of the AD7660. TPC 8 gives the THD versus frequency that the driver should preferably exceed. The AD8519, OP162, or the OP184 meet these requirements and are usually appropriate for almost all applications. As an alternative, in very high-speed and noise-sensitive applications, the AD829 with an external compensation capacitor of 82 pF can be used. This capacitor should have good linearity as an NPO ceramic or mica type. Moreover, the use of a noninverting +1 gain arrangement is recommended and helps to obtain the best signal-to-noise ratio.
Voltage Reference Input
-55
-60
PSRR - dB
-65
-70
-75
-80 1k
10k 100k INPUT FREQUENCY - Hz
1M
Figure 9. PSRR vs. Frequency
POWER DISSIPATION VS. THROUGHPUT
The AD7660 uses an external 2.5 V voltage reference. The voltage reference input REF of the AD7660 has a dynamic input impedance. Therefore, it should be driven by a low impedance source with an efficient decoupling between REF
The AD7660 automatically reduces its power consumption at the end of each conversion phase. During the acquisition phase, the operating currents are very low which allows a significant power saving when the conversion rate is reduced as shown in Figure 10. This feature makes the AD7660 ideal for very lowpower battery applications. It should be noted that the digital interface remains active even during the acquisition phase. To reduce the operating digital supply currents even further, the digital inputs need to be driven close to the power rails (i.e., DVDD and DGND for all inputs except EXT/INT, INVSYNC, INVSCLK, RDC/SDIN, and OVDD or OGND for the last four inputs.
REV. 0
-13-
AD7660
100
POWER DISSIPATION - mW
10
be designed with special care with fast, clean edges and levels, with minimum overshoot and undershoot or ringing. For applications where the SNR is critical, the CNVST signal should have a very low jitter. Some solutions to achieve this are to use a dedicated oscillator for CNVST generation or, at least, to clock it with a high frequency low jitter clock as shown in Figure 6. For other applications, conversions can be automatically initiated. If CNVST is held low when BUSY is low, the AD7660 controls the acquisition phase and then automatically initiates a new conversion. By keeping CNVST low, the AD7660 keeps the conversion process running by itself. It should be noted that the analog input has to be settled when BUSY goes low. Also, at power-up, CNVST should be brought low once to initiate the conversion process. In this mode, the AD7660 could sometimes run slightly faster than the guaranteed limit of 100 kSPS.
DIGITAL INTERFACE
1
0.1
0.01 10
100
1000 THROUGHPUT - SPS
10000
100000
Figure 10. Power Dissipation vs. Sample Rate
CONVERSION CONTROL
Figure 11 shows the detailed timing diagrams of the conversion process. The AD7660 is controlled by the signal CNVST which initiates conversion. Once initiated, it cannot be restarted or aborted, even by the power-down input PD, until the conversion is complete. The CNVST signal operates independently of CS and RD signals. For a true sampling application, the recommended operation of the CNVST signal is the following: CNVST must be held high from the previous falling edge of BUSY, and during a minimum delay corresponding to the acquisition time t8; then, when CNVST is brought low, a conversion is initiated and BUSY signal goes high until the completion of the conversion. Although CNVST is a digital signal, it should
The AD7660 has a versatile digital interface; it can be interfaced with the host system by using either a serial or parallel interface. The serial interface is multiplexed on the parallel data bus. The AD7660 digital interface also accommodates both 3 V or 5 V logic by simply connecting the OVDD supply pin of the AD7660 to the host system interface digital supply. Finally, by using the OB/2C input pin, both two's complement or straight binary coding can be used. The two signals CS and RD control the interface. CS and RD have a similar effect because they are OR'd together internally. When at least one of these signals is high, the interface outputs are in high impedance. Usually, CS allows the selection of each AD7660 in multicircuits applications and is held low in a single AD7660 design. RD is generally used to enable the conversion result on the data bus.
t2 t1
CNVST
BUSY
t3 t5
MODE ACQUIRE
t4 t6
CONVERT ACQUIRE CONVERT
t7
t8
Figure 11. Basic Conversion Timing
t9
RESET
BUSY
DATA
t8
CNVST
Figure 12. RESET Timing
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REV. 0
AD7660
PARALLEL INTERFACE
The AD7660 is configured to use the parallel interface when the SER/PAR is held low. The data can be read either after each conversion, which is during the next acquisition phase, or during the following conversion as shown, respectively, in Figure 14 and Figure 15. When the data is read during the conversion, however, it is recommended, that it is read only during the first half of the conversion phase. That avoids any potential feedthrough between voltage transients on the digital interface and the most critical analog conversion circuitry.
SERIAL INTERFACE
MASTER SERIAL INTERFACE Internal Clock
The AD7660 is configured to generate and provide the serial data clock SCLK when the EXT/INT pin is held low. The AD7660 also generates a SYNC signal to indicate to the host when the serial data is valid. The serial clock SCLK and the SYNC signal can be inverted if desired. The output data is valid on both the rising and falling edge of the data clock. Depending on RDC/ SDIN input, the data can be read after each conversion, or during the following conversion. Figure 16 and Figure 17 show the detailed timing diagrams of these two modes. Usually, because the AD7660 has a longer acquisition phase than the conversion phase, the data is read immediately after conversion. That makes the mode master, read after conversion, the most recommended serial mode when it can be used. In read-after-conversion mode, it should be noted that, unlike in other modes, the signal BUSY returns low after the 16 data bits are pulsed out and not at the end of the conversion phase
The AD7660 is configured to use the serial interface when the SER/PAR is held high. The AD7660 outputs 16 bits of data, MSB first, on the SDOUT pin. This data is synchronized with the 16 clock pulses provided on the SCLK pin.
CS = RD = 0
t1
CNVST
t 10
BUSY
t3
DATA BUS
t4 t 11
PREVIOUS CONVERSION DATA NEW DATA
Figure 13. Master Parallel Data Timing for Reading (Continuous Read)
CS
RD
BUSY
DATA BUS
CURRENT CONVERSION
t 12
t 13
Figure 14. Slave Parallel Data Timing for Reading (Read after Convert)
CS = 0
t1
CNVST, RD
BUSY
t4 t3
DATA BUS
PREVIOUS CONVERSION
t 12
t 13
Figure 15. Slave Parallel Data Timing for Reading (Read During Convert)
REV. 0
-15-
AD7660
which results in a longer BUSY width. In read-during-conversion mode, the serial clock and data toggle at appropriate instants, which minimizes potential feedthrough between digital activity and the critical conversion decisions.
SLAVE SERIAL INTERFACE External Clock
diagrams of these methods. Usually, because the AD7660 has a longer acquisition phase than the conversion phase, the data are read immediately after conversion. While the AD7660 is performing a bit decision, it is important that voltage transients not occur on digital input/output pins or degradation of the conversion result could occur. This is particularly important during the second half of the conversion phase because the AD7660 provides error correction circuitry that can correct for an improper bit decision made during the first half of the conversion phase. For this reason, it is recommended that when an external clock is being provided, it is a discontinuous clock that is toggling only when BUSY is low or, more importantly, that it does not transition during the latter half of BUSY high.
The AD7660 is configured to accept an externally supplied serial data clock on the SCLK pin when the EXT/INT pin is held high. In this mode, several methods can be used to read the data. When CS and RD are both low, the data can be read after each conversion or during the following conversion. The external clock can be either a continuous or discontinuous clock. A discontinuous clock can be either normally high or normally low when inactive. Figure 18 and Figure 20 show the detailed timing
EXT/INT = 0
CS, RD
RDC/SDIN = 0
INVSCLK = INVSYNC = 0
t3
CNVST
BUSY
t 28 t 30 t 29
SYNC
t 25 t 18 t 19 t 20 t 21
1 2 3 14 15
t 14
t 24
16
t 26 t 27
SCLK
t 15
SDOUT X D15 D14 D2 D1 D0
t 16
t 22
t 23
Figure 16. Master Serial Data Timing for Reading (Read after Convert)
EXT/INT = 0 CS, RD
RDC/SDIN = 1
INVSCLK = INVSYNC = 0
t1
CNVST
t3
BUSY
t 17
SYNC
t 25 t 19 t 20 t 21
1 2 3 14 15 16
t 14
t 24
SCLK
t 15 t 18
t 26
t 27
D15 D14 D2 D1 D0
SDOUT
X
t 16
t 22
t 23
Figure 17. Master Serial Data Timing for Reading (Read Previous Conversion During Convert)
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REV. 0
AD7660
CS, RD EXT/INT = 1 INVSCLK = 0
BUSY
t 35 t 36 t 37
SCLK 1 2 3 14 15 16 17 18
t 31
SDOUT X D15
t 32
D14 D13 D1 D0 X15 X14
t 16
SDIN
t 34
X15 X14 X13 X1 X0 Y15 Y14
t 33
Figure 18. Slave Serial Data Timing for Reading (Read after Convert)
External Discontinuous Clock Data Read after Conversion
This mode is the most recommended of the serial slave modes. Figure 18 shows the detailed timing diagrams of this method. After a conversion is complete, indicated by BUSY returning low, the result of this conversion can be read while both CS and RD are low. The data is shifted out, MSB first, with 16 clock pulses and is valid on both rising and falling edge of the clock. Among the advantages of this method, the conversion performance is not degraded because there is no voltage transients on the digital interface during the conversion process. Another advantage is to be able to read the data at any speed up to 40 MHz which accommodates both slow digital host interface and the fastest serial reading. Finally, in this mode only, the AD7660 provides a "daisy chain" feature using the RDC/SDIN input pin for cascading multiple converters together. This feature is useful for reducing component count and wiring connections when it is desired as it is, for instance, in isolated multiconverters applications. An example of the concatenation of two devices is shown in Figure 19. Simultaneous sampling is possible by using a common CNVST signal. It should be noted that the RDC/SDIN input is latched on the opposite edge of SCLK of the one used to shift out the data on SDOUT. Hence, the MSB of the "upstream" converter just follows the LSB of the "downstream" converter on the next SCLK cycle. Up to twenty AD7660s running at 100 kSPS can be "daisy chained" using this method.
BUSY OUT BUSY
BUSY
AD7660
#2 (UPSTREAM) RDC/SDIN SDOUT CNVST CS SCLK SCLK IN CS IN CNVST IN
AD7660
#1 (DOWNSTREAM) RDC/SDIN SDOUT CNVST CS SCLK DATA OUT
Figure 19. Two AD7660s in a "Daisy Chain" Configuration
External Clock Data Read During Conversion
Figure 20 shows the detailed timing diagrams of this method. During a conversion, while both CS and RD are low, the result of the previous conversion can be read. The data is shifted out, MSB first, with 16 clock pulses, and is valid on both rising and falling edges of the clock. The 16 bits have to be read before the current conversion is complete. If that is not done, RDERROR is pulsed high and can be used to interrupt the host interface to prevent incomplete data reading. There is no "daisy chain" feature in this mode, and RDC/SDIN input should always be tied either high or low. To reduce performance degradation due to digital activity, a fast discontinuous clock of 18 MHz at least is recommended to ensure that all the bits are read during the first half of the conversion phase. For this reason, this mode is more difficult to use.
REV. 0
-17-
AD7660
CS, RD EXT/INT = 1 INVSCLK = 0
CNVST
BUSY
t3
t 35 t 36 t 37
1 2 3 14 15 16
SCLK
t 31
SDOUT X D15
t 32
D14 D13 D1 D0
t 16
Figure 20. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert)
MICROPROCESSOR INTERFACING ADSP-21065L in Master Serial Interface
The AD7660 is ideally suited for traditional dc measurement applications supporting a microprocessor, and ac signal processing applications interfacing to a digital signal processor. The AD7660 is designed to interface either with a parallel 16bit-wide interface or with a general purpose serial port or I/O ports on a microcontroller. A variety of external buffers can be used with the AD7660 to prevent digital noise from coupling into the ADC. The following sections illustrate the use of the AD7660 with an SPI equipped microcontroller, the ADSP21065L and ADSP-218x signal processors.
SPI Interface (MC68HC11)
As shown in Figure 22, the AD7660 can be interfaced to the ADSP-21065L using the serial interface in master mode without any glue logic required. This mode combines the advantages to reduce the wire connections and to be able to read the data during or after conversion at user convenience. The AD7660 is configured for the internal clock mode (EXT/INT low) and acts, therefore, as the master device. The convert command can be generated by either an external low jitter oscillator or, as shown, by a FLAG output of the ADSP-21065L or by a frame output TFS of one serial port of the ADSP-21065L which can be used like a timer. The serial port on the ADSP-21065L is configured for external clock (IRFS = 0), rising edge active (CKRE = 1), external late framed sync signals (IRFS = 0, LAFS = 1, RFSR = 1) and active high (LRFS = 0). The serial port of the ADSP-21065L is configured by writing to its receive control register (SRCTL)--see ADSP-2106x SHARC User's Manual. Because the serial port, within the ADSP-21065L will be seeing a discontinuous clock, an initial word reading has to be done after the ADSP-21065L has been reset to ensure that the serial port is properly synchronized to this clock during each following data read operation.
DVDD
Figure 21 shows an interface diagram between the AD7660 and an SPI-equipped microcontroller like the MC68HC11. To accommodate the slower speed of the microcontroller, the AD7660 acts as a slave device and data must be read after conversion. This mode also allows the "daisy chain" feature. The convert command could be initiated in response to an internal timer interrupt. The reading of output data, one byte at a time, if necessary, could be initiated in response to the end-of-conversion signal (BUSY going low) using an interrupt line of the microcontroller. The Serial Peripheral Interface (SPI) on the MC68HC11 is configured for master mode (MSTR) = 1, Clock Polarity Bit (CPOL) = 0, Clock Phase Bit (CPHA) = 1 and SPI interrupt enable (SPIE) = 1 by writing to the SPI Control Register (SPCR). The IRQ is configured for edge-sensitive-only operation (IRQE = 1 in OPTION register).
DVDD
OVDD OR OGND
AD7660*
SER/PAR RDC/SDIN RD EXT/INT SYNC SDOUT SCLK CNVST
ADSP-21065L*
SHARC
RFS DR RCLK FLAG OR TFS
AD7660*
OVDD SER/PAR EXT/INT CS RD BUSY SDOUT SCLK INVSCLK CNVST IRQ
MC68HC11*
CS INVSYNC INVSCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
MISO/SDI SCK I/O PORT
Figure 22. Interfacing to the ADSP-21065L Using the Serial Master Mode
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 21. Interfacing the AD7660 to SPI Interface
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REV. 0
AD7660
APPLICATION HINTS Bipolar and Wider Input Ranges
In some applications, it is desired to use a bipolar or wider analog input range like, for instance, 10 V, 5 V or 0 V to 5 V. Although the AD7660 has only one unipolar range, by simple modifications of the input driver circuitry, bipolar and wider input ranges can be used without any performance degradation. Figure 23 shows a connection diagram which allows that. Component values required and resulting full-scale ranges are shown in Table II.
Table II. Component Values and Input Ranges
It is recommended to avoid running digital lines under the device as these will couple noise onto the die. The analog ground plane should be allowed to run under the AD7660 to avoid noise coupling. Fast switching signals like CNVST or clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and should never run near analog signal paths. Crossover of digital and analog signals should be avoided. Traces on different but close layers of the board should run at right angles to each other. This will reduce the effect of feedthrough through the board. The power supply lines to the AD7660 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. Good decoupling is also important to lower the supplies impedance presented to the AD7660 and reduce the magnitude of the supply spikes. Decoupling ceramic capacitors, typically 100 nF, should be placed on each power supplies pins AVDD, DVDD and OVDD close to, and ideally right up against these pins and their corresponding ground pins. Additionally, low ESR 10 F capacitors should be located in the vicinity of the ADC to further reduce low frequency ripple. The DVDD supply of the AD7660 can be either a separate supply or come from the analog supply, AVDD, or from the digital interface supply, OVDD. When the system digital supply is noisy, or fast switching digital signals are present, it is recommended if no separate supply available, to connect the DVDD digital supply to the analog supply AVDD through an RC filter as shown in Figure 6, and connect the system supply to the interface digital supply OVDD and the remaining digital circuitry. When DVDD is powered from the system supply, it is useful to insert a bead to further reduce high-frequency spikes. The AD7660 has five different ground pins; INGND, REFGND, AGND, DGND, and OGND. INGND is used to sense the analog input signal. REFGND senses the reference voltage and should be a low impedance return to the reference because it carries pulsed currents. AGND is the ground to which most internal ADC analog signals are referenced. This ground must be connected with the least resistance to the analog ground plane. DGND must be tied to the analog or digital ground plane depending on the configuration. OGND is connected to the digital system ground.
Evaluating the AD7660 Performance
Input Range 10 V 5 V 0 V to -5 V
R1 1 k 2 k 8 k
R2 8 k 8 k 8 k
R3 10 k 10 k None
R4 84 k 6.67 k 0
CF R1 R2 U1 IN
ANALOG INPUT
AD7660
U2 R3 R4 100nF INGND 2.5V REF CREF 100nF REFGND REF
Figure 23. Using the AD7660 in 16-Bit Bipolar and/or Wider Input Ranges
For applications where accurate gain and offset are desired, they can be calibrated by acquiring a ground and a voltage reference using an analog multiplexer U2 as shown in Figure 23. Also, CF can be used as a one-pole antialiasing filter.
Layout
The AD7660 has very good immunity to noise on the power supplies as can be seen in Figure 9. However, care should still be taken with regard to grounding layout. The printed circuit board that houses the AD7660 should be designed so the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be easily separated. Digital and analog ground planes should be joined in only one place, preferably underneath the AD7660, or, at least, as close as possible to the AD7660. If the AD7660 is in a system where multiple devices require analog to digital ground connections, the connection should still be made at one point only, a star ground point, which should be established as close as possible to the AD7660.
A recommended layout for the AD7660 is outlined in the evaluation board for the AD7660. The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the Eval-Control Board.
REV. 0
-19-
AD7660
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
48-Lead Quad Flatpack (LQFP) (ST-48)
0.067 (1.70) 0.059 (1.50) 0.055 (1.40) 0.028 (0.7) 0.020 (0.5) 0.012 (0.3) SEATING PLANE
0.362 (9.19) 0.354 (9.00) SQ 0.346 (8.79)
3 37 6 25 24
0.039 (1.00) REF
TOP VIEW
(PINS DOWN)
0.280 (7.1) 0.276 (7.0) SQ 0.272 (6.9)
0.006 (0.15) 0.004 (0.10) 0.002 (0.05) 0.007 (0.177) 0.005 (0.127) 0.004 (0.107)
0 MIN
48 1 12
13
0.023 (0.58) 0.010 (0.26) 0.020 (0.50) 0.007 (0.18) 0.017 (0.42) 0.006 (0.15) 7 3.5 0
0.057 (1.45) 0.055 (1.40) 0.053 (1.35)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS
-20-
REV. 0
PRINTED IN U.S.A.
C01928-2.5-7/00 (rev. 0)

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